1. Field of the Invention
Embodiments of the present invention generally relate to an improved implementation of clocked standby mode in a digital circuit.
2. Description of the Related Art
Integrated circuit (IC) devices often operate using various internally generated voltages in an effort to reduce sensitivity to fluctuating external voltage supplies. Each internally generated voltage may also be used to perform different functions required by the IC. A voltage generation circuit may be used to generate each necessary internal voltage. A typical memory device, such as a dynamic random access memory (DRAM) device may include many such voltage generation circuits, configured to generate a wide variety of voltages, which may include voltages that are positive with respect to a ground reference (e.g., a boosted wordline voltage or VPP) and voltages that are negative with respect to a ground reference (e.g., a back-bias voltage, VBB, or negative wordline voltage, VNWL)
Each voltage generation circuit on a given device may consume power while generating a voltage. In order to conserve the overall power consumed by the IC device, the voltage generation circuit may be placed in a mode (referred to as a standby mode) where the circuit is selectively enabled and disabled. The voltage generation circuit may be enabled while the required voltage is being used by the IC device (e.g., to maintain the generated voltage). For instance, if the IC device is a memory device, the voltage generation circuit may be enabled while the memory device is using the output of the voltage generation circuit to perform an access (e.g., a read or write). While the voltage generation circuit is enabled, the voltage generation circuit may consume power and maintain the required voltage. When the memory device is not being accessed, the voltage generation circuit may be disabled. While the voltage generation circuit is disabled, the circuit may consume less power and the required voltage may not be generated. Because each access to the memory device may be timed according to a clock signal (e.g., each access to the memory device may occur on the rising edge of the clock signal), the clock signal may be used to selectively enable and disable the voltage generation circuit just prior to the access. Accordingly, the standby mode may be referred to as a clocked standby mode (CSM).
FIG. 1 is a block diagram depicting an exemplary memory device 100 which utilizes a clocked standby mode. The memory device 100 may have control circuits 102 used to access one or more memory arrays 104 of the memory device 100. The control circuits 102 may have several internal circuits which may be used to configure and control the memory device. For instance, the control circuits 102 may have clock circuitry 106 for generating various clock signals and a temperature sensor 108 which may be used to measure the temperature of the memory device 100.
The memory device 100 may contain voltage generation circuit(s) 112 which supply internally generated voltage(s) (VOUT(S), V1, V2, . . . VX) to the control circuits 102 and memory arrays 104 of the memory device 100. Each internally generated voltage V1, V2, . . . Vx may be generated as a function of a reference voltage. The reference voltage may be generated by a reference voltage generator and may be used by the control circuits 102 to access (e.g., read, write or refresh) memory arrays 104. The voltage generation circuit(s) 112 may be selectively enabled and disabled by clocked standby mode controls 114. In some cases, the clocked standby mode controls 114 may be enabled or disabled by the control circuits 102. In other cases, the clocked standby mode controls 114 may be permanently enabled such that an enabling signal is not used, or may be permanently enabled by blowing a fuse such as a laser fuse or electronically programmable fuse (e-fuse) of the memory device 100.
FIG. 2 is a block diagram depicting exemplary clocked standby mode controls 114 which are used to selectively enable one or more voltage generation circuits 112. The inputs to the clocked standby mode controls may be a base clock signal (referred to as Base_CLK) and a signal to enable the clocked standby mode (referred to as CSM_EN). When CSM_EN is a high logic value, the clocked standby mode may be enabled, and the clocked standby mode circuits may use the base clock signal to generate a clocked standby mode clock signal (referred to as CSM_CLK) which selectively enables and disables the voltage generation circuits 112. When CSM_EN is a certain value (e.g., a low logic value), the clocked standby mode may be disabled, meaning that the voltage generation circuits 112 may constantly generate voltage. When the clocked standby mode is disabled, the CSM_CLK signal may be set to a constant value (e.g., a low logic value) in order to constantly enable the voltage generation circuits 112.
FIG. 3 is a circuit diagram depicting an exemplary voltage generation circuit 112. The voltage generation circuit may have circuitry 310 for generating a reference voltage (referred to as VREF) which may then be used by a voltage regulator 320 to generate an output voltage (referred to as VOUT). When the voltage generator is enabled (e.g., when the CSM_CLK signal is a low logic value), switches S1 302, S2 308, and S3 318 may be closed while switch S4 312 may be open, allowing current to flow through the voltage generation circuit 112 and generating output voltage VOUT from reference voltage VREF as described below.
If CSM_CLK changes from a low logic value to a high logic value, the voltage generator 112 may be disabled. When the voltage generator is disabled, switches S1 302, S2 308, and S3 318 may be open while switch S4 312 may be closed. When switches S1 302, S2 308, and S3 318 are open, the voltage generation circuit 112 may consume less power. When the voltage generation circuit 112 is disabled, VOUT may be electronically isolated from other voltages in the memory device 100 by switches S3 318 and S4 312. When an output voltage is isolated from other voltages in a circuit, the output voltage is referred to as a floating output voltage. While the voltage generation circuit is disabled, capacitance on the output line may maintain the output voltage near a given level (e.g., VOUT at the time the voltage generation circuit is disabled) until the voltage generation circuit 112 is enabled again by CSM_CLK switching from the high logic value to a low logic value.
FIG. 4 is a timing diagram which depicts the effect of the clocked standby mode on the output voltage VOUT of a voltage generation circuit 112. At time T1, the CSM_EN signal may be a low logic value, indicating that the clocked standby mode is disabled. Accordingly, the signal CSM_CLK generated by the clocked standby mode controls 114 may be set at a low logic level, enabling the voltage generation circuit 112 and maintaining VOUT at a constant level. While the voltage generation circuit 112 is enabled, the base clock signal Base_CLK may have no effect on the CSM_CLK signal.
At some time later, T2, the CSM_EN signal may be raised to a high logic level, enabling the clocked standby mode. When the CSM_EN signal is raised, the clocked standby mode controls 114 may assert the CSM_CLK signal to a high logic value, causing the voltage generation circuit 112 to be disabled, thereby floating VOUT. While the CSM_EN signal is raised, the clocked standby mode controls 114 may generate CSM_CLK using the Base_CLK signal. Thus, at some time later, T3, when a rising edge of Base_CLK is detected, the CSM_CLK signal may be lowered to a low logic level, causing the voltage generation circuit 112 to be enabled again and causing VOUT to be actively generated by the voltage generation circuit 112.
As described above, the rising edge of Base_CLK may be used to enable the voltage generation circuit 112 because the rising edge of Base_CLK may correspond to accesses (e.g., a read or write) to the memory device 100. During each access, the voltage VOUT generated by the voltage generation circuit 112 may be used by the control circuits 102 to access the memory arrays 104. During the period when VOUT is being used, the voltage generation circuits actively generate and regulate VOUT so that the load on VOUT from the memory device 100 does not cause VOUT to fall below a critical level.
After each rising edge of Base_CLK, the CSM_CLK signal may be lowered for a set time, referred to as the pulse width time, TPW. After the time TPW has expired, the CSM_CLK signal may again be asserted, causing the voltage generation circuit 112 to be disabled again. The process of asserting and lowering CSM_CLK may be continued for each rising edge of the Base_CLK as long as the CSM_EN signal is asserted. Thus, the period of the Base_CLK (TBASE) as well as the pulse width TPW of CSM_CLK determine when the voltage generation circuit 112 is disabled and for how long.
While the voltage generation circuit 112 is disabled and VOUT is floating, VOUT may not remain at the exact value which is originally floated by the disabled voltage generation circuit 112. Each time the voltage generation circuit 112 is disabled, secondary effects, such as leakage currents, may slowly degenerate VOUT, even if VOUT is electrically isolated using switches S1 302, S2 308, S3 318, and S4 312. This degeneration in VOUT is indicated in FIG. 4 as VDROOP. The degeneration begins each time the voltage generation circuit 112 is disabled and lasts until the voltage generation circuit 112 is enabled by the rising edge of Base_CLK and the corresponding lowering of the CSM_CLK signal. Each time the voltage generation circuit 112 is enabled, it may take a finite amount of time for the voltage generation circuit 112 to correct VOUT by driving it back to the VREF level. The larger the magnitude of VDROOP is, the longer it may take for the voltage generation circuit 112 to restore VOUT. Because TBASE and TPW may be used to control how long the voltage generation circuit 112 is disabled, TBASE and TPW also affect the magnitude of VDROOP and the corresponding time required for the voltage generation circuit 112 to drive VOUT back to an appropriate level.
Because VOUT is used by other circuits in the memory device 100, it may be important that VOUT not fall below a critical level. If VOUT droops too low, the other circuits which use VOUT may not function properly. For instance, if VOUT is used to refresh the memory arrays 104 and VOUT falls below a critical level, the memory arrays 104 may not be properly refreshed and data in the memory arrays 104 may be lost. Thus, TBASE and TPW may be designed so the magnitude of VDROOP does not become too large and so the voltage generation circuit 112 is enabled long enough to drive VOUT back to the appropriate level needed to operate the memory device 100. Similarly, TBASE and TPW may be chosen so that the time for which the voltage generation circuit 112 is disabled (calculated as TBASE−TPW) is short enough so that VOUT does not drop below an unacceptable level.
In some cases, as the device operates, variations in the operating characteristics of the device may cause larger voltage droops in VOUT. For instance, the period TBASE of the Base_CLK signal may vary with the temperature of the memory device 100. If the temperature of the memory device 100 causes TBASE to increase, the voltage generation circuit 112 may be disabled for a longer period and the magnitude VDROOP may become larger. In another instance, the size of the leakage currents which affect VDROOP may vary with the temperature of the memory device. For example, for some temperature ranges, the leakage currents may increase, causing a corresponding increase in the magnitude of VDROOP. Thus, the variations in the operating characteristics of the memory device 100 may cause VOUT to droop so far that the voltage generation circuit 112 cannot drive VOUT back to the appropriate level needed to operate the memory device 100, causing the memory device 100 to malfunction.
Accordingly, what is needed are improved methods and apparatuses for enabling and disabling a voltage generation circuit.